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holt integrated circuits www.holtic.com 1 july 2011 hi-8596 single-rail arinc 429 differential line driver ds8596 rev. b. 07/11 pin configuration (top view) HI-8596PSI hi-8596pst ampb 1 txbout 2 tx0in 3 tx1in 4 cp- 5 cp+ 6 vdd2p 7 vdd 8 16 ampa 15 txaout 14 - 13 slp 12 cn+ 11 cn- 10 vdd2n 9 gnd 1 6 - p i n p l a s t i c s o i c p a c k a g e ( n a r r o w b o d y ) ( see page 9 for additional package pin confgurations ) table 1. function table tx1in tx0in slp txaout txbout slope 0 0 x 0v 0v n/a 0 1 0 -5v 5v 10s 0 1 1 -5v 5v 1.5s 1 0 0 5v -5v 10s 1 0 1 5v -5v 1.5s 1 1 x hi-z hi-z n/a general description the hi-8596 bus interface product is a silicon gate cmos device designed as a line driver in accordance with the arinc 429 bus specifcations. the part includes a dual polarity voltage doubler, allowing it to operate from a single +3.3v supply using only four external ca - pacitors. the part also features high-impedance outputs (tri-state) when both data inputs are taken high, allowing multiple line drivers to be connected to a common bus. logic inputs feature built-in 4kv esd input protection (hbm) as well as 5v or 3.3v logic level compatibility. 37.5 ohm or 5 ohm resistors in series with each arinc output are available to allow the use of external resistors for lightning protection. the hi-8596 line driver is intended for use where logic signals must be converted to arinc 429 levels such as when using an fpga or the hi-3586 arinc 429 protocol ic. the part is available in industrial -40 o c to +85 o c, or extended, -55 o c to +125 o c temperature ranges. optional burn-in is available on the extended temperature range. features ? single +3.3v supply ? all arinc 429 voltage levels generated on-chip ? digitally selectable rise and fall times ? tri-state outputs ? 5 ohm or 37.5 ohm output resistance ? industrial and extended temperature ranges ? burn-in available
hi-8596 holt integrated circuits 2 block diagram current control -5v 5v one null zero control logic txbout -5v 5v slp esd protection & voltage translation tx0in tx1in one null zero a side ampa 3.3v v dd gnd 5 ohms ampb v dd dual polarity voltage doubler vdd2+ txaout vdd2+ cp+ cp- c fly cn+ cn- c fly c supply control logic current control b side 37.5 ohms 5 ohms 37.5 ohms c out vdd2- vdd2- c out vdd2- vdd2+ figure 1. hi-8596 block diagram
hi-8596 holt integrated circuits 3 pin descriptions table 2. pin descriptions pin function description slp input output slew rate control. high selects arinc 429 high-speed. low selects arinc 429 low-speed. tx0in input data input zero tx1in input data input one v dd power +3.3v power supply gnd power ground supply v dd2+ output voltage doubler positive output (~6.6v for 3.3v supply) cp+ analog v dd2+ fyback capacitor, c fly ; positive terminal cp- analog v dd2+ fyback capacitor, c fly ; negative terminal v dd2- output voltage doubler negative output (~ -6.6v for 3.3v supply) cn+ analog v dd2- fyback capacitor, c fly ; positive terminal cn- analog v dd2- fyback capacitor, c fly ; negative terminal txaout output arinc high output with 37.5 ohms series resistance ampa output arinc high output with 5 ohms series resistance txbout output arinc low output with 37.5 ohms series resistance ampb output arinc low output with 5 ohms series resistance
hi-8596 holt integrated circuits 4 functional description figure 1 is a block diagram of the line driver. the hi-8596 requires only a single +3.3v power supply. an integrated inverting / non-inverting voltage doubler generates the rail voltages (6.6v) which are then used to produce the 5v arinc-429 output levels. the internal dual polarity charge pump circuit requires four external capacitors, two for each polarity gener - ated by the doubler. cp+ and cp- connect the exter - nal charge transfer or fy capacitor, c fly , to the positive portion of the doubler, resulting in twice v dd at the v dd2+ pin. an output hold capacitor, c out , is placed between v dd2+ and gnd. c out should be ten times the size of c fly . the inverting or negative portion of the converter works in a similar fashion, with c fly and c out placed between cn+ / cn- and v dd2- / gnd respectively. currents for slope control are set by on-chip resistors. the tx0in and tx1in inputs receive logic signals from a control transmitter chip such as the hi-3584. txaout and txbout hold each side of the arinc bus at ground until one of the inputs becomes a one. if for example tx1in goes high, a charging path is enabled to 5v on an a side internal capacitor while the b side is enabled to -5v. the charging current is selected by the slp pin. if the slp pin is high, the capacitor is nominally charged from 10% to 90% in 1.5s. if slp is low, the rise and fall times are 10s. a unity gain buffer receives the internally generated slopes and differentially drives the arinc line. cur - rent is limited by the series output resistors at each pin. there are no fuses at the outputs of the hi-8596. the hi-8596 has 37.5 ohms in series with each txout output and 5 ohms in series with each amp output. the amp outputs are for applications where external series resistance is required, typically for lightning protection devices. holt application note an-300 describes suit - able lightning protection schemes. tri-stateable outputs allow multiple line drivers to be connected to the same arinc 429 bus. setting tx1in and tx0in both to a logic 1 puts the outputs in the high-impedance state. absolute maximum ratings supply voltages v dd .......................................................... +5v power dissipation at 25 o c plastic soic ........... 1.0w, derate 10mw/ o c ceramic dip ......... 0.5w, derate 7mw/ o c solder temperature ......................... 275 o c for 10sec storage temperature ....................... -65 o c to +150 o c note: heat sink on qfn package the hi-8596 driver is available in a small-footprint, thermally enhanced qfn (chip-scale) package. this package includes an electrically isolated metal heat sink located on the bottom surface of the device. this heat sink should be soldered down to the printed circuit board for optimum thermal dissipation. recommended operating conditions supply voltages v dd ................................... +3.0v to +3.6v temperature range industrial screening .............. -40 o c to +85 o c hi-temp screening .............. -55 o c to +125 o c note: stresses above absolute maximum ratings or outside recom - mended operating conditions may cause permanent damage to the device. these are stress ratings only. operation at the limits is not recommended.
hi-8596 holt integrated circuits 5 electrical characteristics table 3. dc electrical characteristics v dd = +3.3v, t a = operating temperature range (unless otherwise stated) parameters symbol test conditions min typ max units input voltage (tx1in, tx0in, slp) high low v ih v il 0.7v dd - - - - 0.3v dd v v input current (tx1in, tx0in, slp) source sink i ih i il v in = 0v v in = 3.3v, 7.34k pulldown - - - 45 0.1 a a arinc output voltage (differential) one zero null v diff1 v diff0 v diffn no load; txaout - txbout no load; txaout - txbout no load; txaout - txbout 9 -11 -0.5 10 -10 0 11 -9 0.5 v v v arinc output voltage (ref. to gnd) one or zero null v dout v nout no load & magnitude at pin no load 4.5 -0.25 5.0 0 5.5 0.25 v v operating supply current no load max. load i ddnl i ddl slp = v dd tx1in & tx0in = 0v 100khz, 400 load - - 28 65 40 - ma ma arinc output impedance txout pins amp pins z out 37.5 5 ohms ohms arinc output tri-state current i oz tx0in = tx1in = v dd -5.75v < v out < +5.75v -1.0 0 +1.0 a
hi-8596 holt integrated circuits 6 table 4. converter characteristics v dd = +3.3v, t a = operating temperature range (unless otherwise stated) parameters symbol test conditions min typ max units start-up transient (v+, v-) t start - - 10 ms operating switching frequency f sw - 650 - khz recommended capacitors c fly c out c supply c out / c fly >= 10 c supply >= c out (connect from v dd to gnd) 2.2 22 47 4.7 47 68 - - - f f f table 5. ac electrical characteristics v dd = +3.3v, t a = operating temperature range (unless otherwise stated) parameters symbol test conditions min typ max units line driver propogation delay output high to low output low to high t phlx t plhx defned in figure 2, no load - - 500 500 - - ns ns line driver transition times high speed output high to low output low to high low speed output high to low output low to high t fx t rx t fx t rx slp = v+ pin 1 = logic 1 pin 1 = logic 1 slp = v+ pin 1 = logic 0 pin 1 = logic 0 1.0 1.0 5.0 5.0 1.5 1.5 10.0 10.0 2.0 2.0 15.0 15.0 s s s s input capacitance (logic) 1 c in - - 10 pf output capacitance (tri-state) 1 c out tx0in = tx1in = v dd - - 10 pf notes: 1. guaranteed but not tested
hi-8596 holt integrated circuits 7 0v 10v -10v 5v 0v 5v 0v 10% 90% t fx 10% 90% t phlx 10% tx1in tx0in v diff (txaout - txbout) t fx t rx t rx t plhx t phlx t plhx figure 2. line driver timing
hi-8596 holt integrated circuits 8 ordering information part number lead finish blank tin / lead (sn / pb) solder f 100% matte tin (pb-free, rohs compliant) part number temperature range flow burn in i -40 o c to +85 o c i no t -55 o c to +125 o c t no m -55 o c to +125 o c m yes part number package description lead finish 8596ps 16 pin plastic small outline - nb soic (16hn) solder 8596pc 16 pin plastic qfn (16pcs) solder hi - 8596 px x x (plastic) part number temperature range flow burn in lead finish i -40 o c to +85 o c i no gold (pb-free, rohs compliant) t -55 o c to +125 o c t no gold (pb-free, rohs compliant) m -55 o c to +125 o c m yes tin / lead (sn / pb) solder part number package description 8596cd 20 pin ceramic side braised dip (20c) hi - 8596 cd x (ceramic)
hi-8596 holt integrated circuits 9 additional pin configurations note: all power and ground pins must be connected. ampb txbout tx1in slp cp- cn+ cp+ cn- vdd2p vdd vdd2n gnd - ampa txaout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 tx0in hi-8596cd 16-pin ceramic side-brazed dip 16 txbout 15 ampb 14 ampa 13 txaout tx0in 1 cp- 3 tx1in 2 cp+ 4 9 cn- 12 - 11 slp 10 cn+ vdd2p 5 vdd 6 gnd 7 vdd2n 8 hi-8596pc 16-lead 4mm x 4mm qfn
hi-8596 holt integrated circuits 10 revision history revision date description of change ds8596, rev. new 11/10/10 initial release rev. a 11/11/10 clarifed connection of heat sink and updated some electrical parameters (v ih , v il , f sw ). added operating supply current at full load (i ddl ). rev. b 7/14/11 updated supply voltage range. corrected dimensions on qfn heat sink. added voltage limits for tri-state output current.
hi-8596 holt integrated circuits 11 package dimensions 16-pin plastic small outline (soic) - nb narrow body) inches (millimeters) package type: 16hn 0 to 8 detail a .0025 .002 (.06 4 .038) .033 .017 (.83 8 .432) .061 .007 (1.54 9 .178) .0165 .003 (.41 9 .089) .390 .004 (9.9 0 .10) .236 .008 (5.99 .20) .0087 .0015 (.22 0 .029) see detai l a .1525 .0025 (3.8 7 .06) to p v iew .050 (1.27) bsc 4.00 bsc 4.00 bsc 2.80 .10 2.80 .10 0.40 . 05 1.00 ma x 0.20 typ 0.65 bsc 0.30 .05 to p v iew bottom v iew electrically isolated heat sink pad on bottom of package. 16-pin plastic chip-scale package (qfn) millimeters package type: 16pcs bsc = basic spacing between centers is theoretical true position dimension and has no tolerance. (jedec standard 95)
hi-8596 holt integrated circuits 12 package type: 16c 16-pin ceramic side-brazed dip base plane sea ting plane .050 .005 (1.270 .127) .295 .010 (7.493 .254) pin 1 .01 8 .002 (.457 .051) .010 .002 (.254 .051) .035 .010 (.889 .254) .810 (20.574) .30 0 .010 (7.620 .254) .100 (2.54) bsc .200 (5.080) ma x .125 (3.175) min ma x inches (millimeters) bsc = basic spacing between centers is theoretical true position dimension and has no tolerance. (jedec standard 95)

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